copyright ? cirrus logic, inc. 2010 (all rights reserved) advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. http://www.cirrus.com may ?10 ds882pb1 ultra low power mobile audio and telephony codec product overview for the full datasheet, visit www.cirrus.com/codec-datasheets/cs42l73 ? stereo adc ? dual analog or digital mic support ? dual mic bias generators ? four dacs coupled to five outputs ? ground-centered stereo headphone amp. ? ground-centered stereo line output ? mono ear speaker amplifier ? mono 1 w speakerphone amplifier ? mono speakerphone line output for stereo speakerphone expansion ? three serial ports with asynchronous sample rate converters ? digital audio mixing and routing ultra low power consumption ? 3.5 mw quiescent headphone playback applications ? smart phones, umpcs, and mids system features ? native (no pll required) support for 6/12/24 mhz, 13/26 mhz, and 19.2/38.4 mhz master clock rates in add. to typ. audio clock rates ? integrated high-efficiency power management reduces power consumption ? internal ldo regulator to reduce internal digital operating voltage to vl/2 ? step-down charge pump provides low headphone/line out supply voltage ? inverting charge pump accommodates low system voltage by pr oviding negative rail for hp and line amp ? flexible speakerphone amplifier powering ? 3.00 v to 5.25 v range ? independent cycling ? power down management ? individual controls for adcs, dig. mic interface, mic bias generators, serial ports, and output amplifiers & associated dacs ? programmable thermal overload notification ? high-speed i2c? control port (400 khz) ( features continued on page 2 ) cs42l73 ` line outputs pseudo diff. input - + +vcp_filt -vcp_filt digital processing level shifters cs42l73 decimator, hpf, noise gate, alc, volume, mute, swap/mono volume, mute, limiter mclk stereo multi-bit ? dac mclk stereo multi-bit ? dac ldo vd_filt headphone outputs pseudo diff. input - + +vcp_filt -vcp_filt ear speaker output va - + b speakerphone line output (right) - + vp b vp speakerphone output (left) - + vp a va va digital mic interface digital mic interface vl mclk stereo multi-bit ? adc -6 to +12 db, 0.5 db steps - + mic 2 mic 1 pseudo diff. input pseudo diff. input line input (left) line input (right) pseudo diff. input +10 or +20 db - + +10 or +20 db - + mic 1 bias mic 2 bias mic bias short detect mic bias audio serial port voice serial port auxiliary serial port audio serial port sdout sdin asrc asrc voice serial port sdout asrc auxiliary serial port sdin asrc sdout asrc sdin asrc -vcp_filt inverting step-down vcp +vcp_filt +vcp_filt -vcp_filt mclk mclk1 mclk2 control port control port vp vd_filt digital mixer volume, mute, limiter mic2_sdet + audio serial port voice serial port auxiliary serial port mic/line input path
2 cs42l73 stereo analog to digital features ? 91 db dynamic range (a-wtd) ? -85 db thd+n ? independent adc channel control ? 2:1 stereo analog input mux ? stereo line input ? shared pseudo-differential reference input ? dual analog mic inputs ? pseudo-diff. or single-ended ? two, independent, programmable, low- noise, mic bias outputs ? mic short detect to support headset button ? analog programmable gain amplifier (pga) (+12 to -6 db in 0.5 db steps) ? +10 db or +20 db analog mic boost in addition to pga gain settings ? programmable automatic level control (alc) ? noise gate for noise suppression ? progr. threshold & attack/release rates dual digital microphone interface ? programable clock rate ? integer divide by 2 or 4 of internal mclk stereo dac to head phone amplifier ? 94 db dynamic range (a-wtd) ? -81 db thd+n into 32 ? integrated step-down/inverting charge pump ? class h amplifier - automatic supply adj. ? high efficiency ?low emi ? pseudo-differential ground-centered outputs ? high hp power output at -70/-81 db thd+n ? 2 x 17/8.5 mw into 16/32 @ 1.8 v ? pop and click suppression ? analog vol. ctl. (+12 to -50 db in 1 db steps; to -76 db in 2 db steps) with zero-cross trans. ? digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions ? programmable peak-detect and limiter stereo dac to line outputs ? 97 db dynamic range (a-wtd) ? -86 db thd+n ? class-h amplifier ? pseudo-differential ground-centered outputs ? 1 v rms line output @ 1.8 v ? pop and click suppression ? analog vol. ctl. (+12 to -50 db in 1 db steps; to -76 db in 2 db steps) with zero-cross trans. ? digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions ? programmable peak-detect and limiter mono dac to ear speak er amplifier ? high power output at -70 db (0.032%) thd+n ? 45 mw into 16 @ 1.8 v ? pop and click suppression ? digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions ? programmable peak-detect and limiter mono dac to speakerph one amplifier ? high output power at 1% thd+n ? 1.18/0.84/0.66 w into 8 @ 5.0/4.2/3.7 v ? direct battery-powered operation ? pop and click suppression ? digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions ? programmable peak-detect and limiter mono dac to speaker ph. line output ? 84 db dynamic range (a-wtd) ? -75 db thd+n ? high voltage (1.53 v rms @ va = 1.8 v, vp = 3.7 v) line output to ensure maximum output from a wide variety of external amplifiers ? pop and click suppression ? digital vol. ctl. (+12 to -102 db in 0.5 db steps) with soft-ramp transitions ? programmable peak-detect and limiter serial ports ? three independent serial ports: auxiliary, audio, and voice ? 8.00, 11.025, 12.00, 16.00, 22.05, 24.00, 32.00, 44.10, and 48.00 khz sample rates ? all ports support master or slave operation with i2s interface ? auxiliary and voice ports support slave operation with pcm interface ? auxiliary and audio ports are stereo- input/stereo-output to/from digital mixer ? voice port is mono-input/stereo-output to/from digital mixer ? integrated asynch. sample rate converters
3 cs42l73 general description the cs42l73 is a highly integrated, low-power, audio and telephony codec for portable applications such as smartphones and ultra mobile personal computers. the cs42l73 features a flexible clocking architecture , allowing the device to utiliz e reference clock frequencies of 6, 12, 24, 13, 26, 19.2, or 38.4 mhz, or any standard aud io master clock. up to two reference/master clock sourc- es may be connected; either one can be selected to driv e the internal clocks and processing rate of the cs42l73. thus, multiple master clock sources within a system can be dynamically activated and de-a ctivated to minimize sys- tem-level power consumption. three asynchronous bidirectional serial ports (auxiliary, audio, and voice serial ports) support multiple clock domains of various digital audio sources or destinat ions. three low-latency, fast-locking, integrated high-perfor- mance asynchronous sample rate converters synchronize and convert the audio samples to the internal processing rate of the cs42l73. a stereo line input or two mono (one stereo) microphone (mic) inputs are routed to a stereo adc . the mic inputs may be selectively pre-amplified by +10 or +20 db. two independent, low-noise mic bias voltage supplies are also provided. a programmable gain amplifier (pga) is applied to the inputs before they reach the adc. the stereo input path that follows the stereo adc begins with a mu ltiplexer to selectivel y choose data from a dig- ital mic interface . following the multip lexer, the data is decimated, select ively dc high-pass filtered, channel- swapped or mono-to-stereo routed (fanned-out), and volume adjusted or muted. the volume levels can be automat- ically adjusted via a programmable automatic level control (alc) and noise gate. a digital mixer is utilized to mix and r oute the cs42l73?s inputs (analog inputs to adc, digital mic, or serial ports) to outputs (dac-fed amplifiers or seri al ports). there is independent attenuat ion on each mixer input for each output. the processing along the output paths from the digital mixer to the two stereo dacs includes volume adjustment and mute control. a peak-detector can be used to automatic ally adjust the volume leve ls via a programmable limiter. the first stereo dac feeds the stereo headphone and line output amplifiers , which are powered from a dedicated positive supply. an integrated charge pump provides a negative supply. this allows a ground-centered analog out- put with a wide signal swing, and elim inates external dc-blocking capacitors while reducing pops and clicks. tri- level class-h amplification is utilized to reduce power cons umption under low-signal-lev el conditions. analog vol- ume controls are provided on the stereo headphone and line outputs. the second stereo dac feeds several mono out puts. the left channel of the dac sources a mono, differential- drive, speakerphone amplifier for driving the handset speakerphone. the right channel sources a mono, differ- ential-drive, earphone amplifier for driving the handset earphone. the right channel is also routed to a mono, differential-drive, speakerphone line output , which may be connected to an external amplifier to implement a ste- reo speakerphone configuration when it is used in conjunction with the integr ated speakerphone amplifier. the cs42l73 implements robust power management to achieve ultra-low power consumption. high granularity in power-down controls allows individual functional blocks to be powered down when unused. the internal low drop- out regulator (ldo) saves power by running the internal digi tal circuits at half the logic interface supply voltage (vl/2). in a system with an existing hi gh-efficiency supply at vl/2, the internal ldo may be disabled and the digital circuits powered directly by the external vl/2 supply. a high-speed i2c control port interface capable of up to 400 khz operation facilit ates register programming. the cs42l73 is available in space-saving 64-ball wlcsp and 65-ball fbga packages for the commercial (-40 to +85 c) grade.
4 cs42l73 1. typical connection diagram optional bias res. dgnd vl scl sda r p asp_lrck applications processor asp_sclk asp_sdin asp_sdout cs42l73 mic2_bias line level out left & right spkout+ spkout- mic2 mic2_ref 2.2 f spk_vq agnd 2.2 f filt+ earout+ earout- vp vbat lineina line in left 100 k lineinb line in right 100 k 0.1 f 4.7 f 2.2 f +vcp_filt flyc flyn -vcp_filt 2.2 f 2.2 f vcp vana flyp 2.2 f hpoutb hpouta 100 33 nf hpout_ref lineoutb lineouta linein_ref vsp_lrck baseband processor mclk1 vsp_sclk vsp_sdin vsp_sdout 2.2 f vd_filt 1 f lineo_ref cpgnd pgnd mic1_bias mic1 mic1_ref r p ana_vq 4.7 f int reset 1 f headphone out left & right 100 33 nf speakerphone (left) ear speaker (receiver) + + + + + r i_p 2200 pf c0g 390 390 2200 pf c0g optional lpf ground ring 0.1 f mclk2 dmic_sd dmic_sclk spklineo+ spklineo- xsp_lrck xsp_sclk xsp_sdin xsp_sdout micb_filt 4.7 f + r bias headset microphone handset microphone 1 f r bias mic2_sdet speakerphone (right) l/r data l/r data bluetooth ? transceiver cellular voice sp aec sp right/data2 digital microphone left/data1 digital microphone vana va 0.1 f pmu usb +5 v vbat ldo switching regulator reset generator +1.8 v +1.8 v vdig vdig vbat class-d cs35l0x + + 1 f 1 f 1 f 0.1 f 0.1 f 0.1 f 0.1 f + + 2.2 f 2.2 f
5 cs42l73 2. package dimensions 2.1 wlcsp package 64 ball wlcsp (3.44 x 3.44 mm body) package drawing millimeters dim min nom max a 0.450 0.505 0.560 a1 0.170 0.200 0.230 a2 0.280 0.305 0.330 m - 2.800 - n - 2.800 - b 0.230 0.260 0.290 c - 0.320 - d - 0.320 - e - 0.400 - x 3.415 3.440 3.465 y 3.415 3.440 3.465 controlling dimension is millimeters. table 1. wlcsp package dimensions notes: 1. controlling dimensions are in millimeters. 2. dimensioning and tolerances per asme y 14.5m-1994. 3. dimension ?b? applies to the solder sphere diameter and is measured at the midpoint between the package body and the seating plane. 4. unless otherwise specified, to lerances are: linear 0.05 mm, angular 1. e e a2 ball a1 location indicator x y bump side side view a1 b n m d c wafer back side ball a1 location indicator (seen through package) ball a1 a
6 cs42l73 2.2 fbga package 65 ball fbga (5x5mm body) pa ckage drawing millimeters dim min nom max a 0.740.871.00 a1 0.16 0.21 0.26 a2 0.58 0.66 0.74 m - 4.00 - n - 4.00 - b 0.270.300.37 c - 0.50 - d - 0.50 - e - 0.50 - x 4.905.005.10 y 4.905.005.10 controlling dimension is millimeters. table 2. fbga package dimensions notes: 1. controlling dimensions are in millimeters. 2. dimensioning and tolerances per asme y 14.5m-1994. 3. dimension ?b? applies to the solder sphere diameter and is measured at the midpoint between the package body and the seating plane. 4. unless otherwise specified, tolerances are: linear 0.05 mm, angular 1. e e a2 ball a1 location indicator x y bump side side view a1 b n m d c top side ball a1 location indicator ball a1 a
7 cs42l73 3. thermal characteristics notes: 1. test printed circuit board asse mbly (pcba) constructed in accordance with jedec standard jesd51-9. two signal, two pla ne (2s2p) pcb utilized. 2. test conducted with still air in accordance with jedec standards jesd51, jesd51-2a, and jesd51-8. 4. ordering information parameter (notes 1 and 2) symbol min typ max units wlcsp package junction to ambient thermal impedance ja -43 -c/watt fbga package junction to ambient thermal impedance ja -58 -c/watt product description package pb-free grade temp range container order # cs42l73 ultra low power mobile audio and telephony codec 64 ball wlcsp yes commercial -40 to +85 c tray cs42l73-cwz tape & reel cs42l73-cwzr 65 ball fbga tray cs42l73-crz tape & reel CS42L73-CRZR contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. important notice ?advance? product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries (?cirrus?) be- lieve that the information contained in this document is accurate and reliable. however, the information is subject to change w ithout notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limit ation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclus ion of cirrus products in such appl ications is understood to be full y at the customer?s risk and cir- rus disclaims and makes no warranty, expres s, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in cr itical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any a nd all liability, including at- torneys? fees and costs, that may result fr om or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a trademark of philips semiconductor. bluetooth is a registered trademark of the bluetooth special interest group (sig).
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